Computing devices use memory devices to store data and code for a processor to execute its operations. As the memory devices decrease in size and increase in density, they experience more errors during processing, referred to as yield issues. Thus, memory devices experience increasing bit failures, even with modern processing techniques. To mitigate bit failures, modern memory devices provide internal error correction mechanisms, such as ECC (error correction codes). The memory devices generate the ECC data internally, and use the ECC data internally at the memory devices. The internal error correction within a memory device can be in addition to whatever system-wide error correction or error mitigation the system is configured to use in data exchanges between the memory devices and the memory controllers.
SBEs (single bit errors) corrected by the memory devices appear to the memory controller or the host system as though there is no error. Thus, if additional errors accumulate in the memory device after manufacturing, the memory device will continue to perform ECC and the increasing number of failures of the memory device may not be visible to the host system. The memory device would traditionally need to identify information about internal error correction to provide information about error accumulation. However, exposing error correction information can provide proprietary information about processes and manufacturing, such as internal error information or details about internal error correction. There are currently no mechanisms to reveal information about the accumulation of errors within a memory device without exposing information about internal error correction.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.